--
-- Copyright 1991-2012 Mentor Graphics Corporation
--
-- All Rights Reserved.
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
-- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
--   

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test_counter is
    Generic(
			  tic_length : integer := 16000
          );
end;

architecture only of test_counter is


component phase_counter
    port (
             clk: IN std_logic;
             thresh0: OUT std_logic;
             q: OUT std_logic_VECTOR(2 downto 0));
end component;
component tic_counter
	port (
	clk: IN std_logic;
	ce: IN std_logic;
	sclr: IN std_logic;
	q: OUT std_logic_VECTOR(13 downto 0));
end component;


SIGNAL clk          : STD_LOGIC := '0';
SIGNAL reset        : STD_LOGIC := '0';
SIGNAL p_th         : STD_LOGIC := '0';
SIGNAL phase_pom    : STD_LOGIC_VECTOR( 2 downto 0 );
signal tic_sclr : std_logic;
signal count_out : std_logic_vector(13 downto 0);

begin

    -- computation phase generator
    phase_count : phase_counter
   PORT MAP(
               clk => clk,
               thresh0 => p_th,
               q       => phase_pom
           );

    -- correlator tic counter
    tic_count: tic_counter
    port map (
                 clk => clk,
                 ce => p_th,
                 sclr => tic_sclr,
                 q => count_out);

    process(clk)
    begin
        if clk'event and clk = '1' then
            if count_out = CONV_STD_LOGIC_VECTOR(tic_length-1, 14) and p_th = '1' then
                tic_sclr <= '1';
                -- tic_no_counter_pom <= tic_no_counter_pom+1; --tic number counter
            else
                tic_sclr <= '0';
            end if;
        end if;
    end process;	



clock : PROCESS
   begin
   wait for 8 ns; clk  <= not clk;
end PROCESS clock;

stimulus : PROCESS
   begin
   wait for 5 ns; reset  <= '1';
   wait for 4 ns; reset  <= '0';
   wait;
end PROCESS stimulus;

end only;

